The present invention relates generally to semiconductor memory devices, and more particularly, to a novel refresh timer for controlling the data retention mode thereof, in response to a number of different operating voltages.
In semiconductor memory devices such as dynamic random access memories (DRAMS) and pseudo DRAMS, a data retention mode of operation is required in order to prevent the loss of data stored in the storage capacitor of each memory cell due to leakage of the storage capacitor and due to leakage current of the substrate over relatively short time intervals. The data retention mode consists of a back bias voltage generating operation for preventing the loss of data due to leakage current of the substrate, and a refresh operation for preventing the loss of data due to leakage of the storage capacitor of each memory cell. The back bias voltage generating operation is performed by applying a back bias voltage to the substrate. The refresh operation is performed by periodically refreshing the data stored in each memory cell. The time period between successive refresh operations is preferably constant, and is commonly referred to as the refresh cycle time.
In general, it is desired to make the refresh cycle time as long as possible in order to reduce current consumption, while simultaneously minimizing the loss of data due to capacitor leakage. It has become increasingly possible to extend the refresh cycle time due to the advent of high integration density DRAMs which use relatively low level external supply voltages. Further, it is desired to make the refresh cycle time as precisely uniform as possible, in order to ensure the accuracy, stability, and reliability of the refresh operation. However, when DRAMs are employed in notebook computers and the like which utilize a battery as a primary or secondary voltage source, it has been deemed advantageous to use at least two separate operating voltages, in order to extend the useful life of the battery and to minimize the likelihood that a system malfunction will occur. In this connection, notebook computers typically employ a battery to supply an initial external supply voltage of 5 V, and then, when a low voltage level condition is detected (e.g., when the battery supply voltage drops below 5 V for a given period of time) due to discharge of the battery during use, the operating voltage is switched to 3.3 V. The transition from a higher operating voltage to a lower operating voltage causes a problem in that the refresh timer currently used in such devices generates a refresh timing signal having a frequency which varies depending upon the level of the operating voltage. Thus, when the operating voltage is switched from the 5 V level to the 3.3 V level, the refresh cycle time is increased, thereby rendering the refresh cycle time non-uniform (i.e., non-constant) between the two operating voltage modes. In this connection, a functional block diagram of a conventional refresh timer is depicted in FIG. 1, and is described below.
More particularly, with reference to FIG. 1, the conventional refresh timer includes a ring oscillator 1 and a counter stage 2, which are operated by a refresh timer enable clock signal .phi./RFH. The signal .phi./RFH goes high in response to a column address strobe signal /CAS (not shown) going high before a row address strobe signal /RAS (not shown) goes high, which condition signifies that a refresh cycle is to be performed. In response to the .phi./RFH signal going high, the ring oscillator 1 generates a pulse .phi.OSC having a period of a few microseconds (.mu.s). Because the period of the pulse .phi.OSC is less than the desired refresh cycle time, it is fed to a counter stage 2 which functions to extend the length of the pulse. In this connection, the output Qi of the counter stage 2 is a pulse having a period equal to the desired refresh cycle time.
With reference now to FIG. 2, there can be seen a chart illustrating the period of the output signal .phi.OSC of the ring oscillator 1 as a function of the operating voltage level. As can be readily appreciated, the output signal .phi.OSC of the ring oscillator 1 has a period which differs dependent upon the level of the operating voltage. For example, when the operating voltage is 3.0 V, the period of .phi.OSC is approximately 2.2 .mu.s, and when the operating voltage is 4.0 V, the period of .phi.OSC is approximately 1.1 .mu.s. Consequently, the refresh cycle time undesirably varies in response to fluctuations and variations of the operating voltage, thereby degrading the reliability, stability, and accuracy of the refresh operation.
Thus, as is evident from the foregoing, there presently exists a need for a refresh timer which eliminates the above-described drawbacks and shortcomings of presently available refresh timers. The present invention fulfills this need.